Prof. Yvon Savaria

Biograph:  Yvon Savaria FIEEE received the B.Ing. and M.Sc.A in electrical engineering from Polytechnique Montreal Canada in 1980 and 1982 respectively. He also received the Ph.D. in electrical engineering in 1985 from McGill University. Since 1985, he has been with Polytechnique Montreal, where he is currently professor and director of the Microelectronics Research Group in the department of electrical engineering. Professor Savaria was also appointed as a guest scientist at the Innovation Institue of Beihang University.

He has carried work in several areas related to microelectronic circuits and microsystems such as testing, verification, validation, physical design methods, defect and fault tolerance, effects of radiation on electronics, CAD methods, reconfigurable computing and applications of microelectronics to telecommunications, aerospace, image processing, video processing, radar signal processing, and digital signal processing acceleration. He is currently involved in several projects that notably relate to virtual networks, machine learning, computational efficiency and application specific architecture design. He used artificial neural networks and a wide range of hardware acceleration techniques to implement effective hardware accelerated signal processors over the past 30 years. He holds 16 patents, has published more than 160 journal papers and more than 460 conference papers.

He has been working as a consultant or was sponsored for carrying research by more than 20 companies or research organizations. He is a member of the Regroupement Stratégique en Microélectronique du Québec (Canada) (RESMIQ), of the Ordre des Ingénieurs du Québec (OIQ - Canada), and is a member of CMC Microsystems Advisory Comittee. He was co-founder of two high-tech spin-offs and an early collaborator to several others. He also received in 2006 a Synergy Award of the Natural Sciences and Engineering Research Council of Canada for his work with LTRIM.

Title:Hardware Support Architectures and Implementations for Effective Embedded AI and Signal Processing

Abstract: Signal Processing and AI algorithms can be very demanding when used in embedded systems with stringent density, power and energy consumption constraints. Hardware accelerators and dedicated architectures are often mandatory to meet system requirements. This talk will review the concept of hardware accelerators, how they can be implemented and what they can contribute to embedded signal processing and AI engines. The benefits can be in terms of throughput, latency, power, energy and system density. Designers can leverage many solutions, ranging from multi-processor, ASIP, ASICs and FPGA based systems on chip.  A global perspective, covering from roots of the field to state-of-the-art methods will be presented. The talk will tap on a long experience developed through dozens of implementations and  applications leveraging diverse technologies.


Important dates

Paper Submission Deadline:
30 April 2019
Extend to 31 May 2019
Paper Acceptance Notification:
15 July 2019
Camera-ready Paper Submission:
15 August 2019
Registration open date:
1 July 2019
Conference Date:
11-13 December, 2019

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